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Analysis and design of embedded DDR bus wiring

Double data rate) design is the most important DDR in embedded hardware design and the most core part. With the processing power of embedded system is getting stronger and stronger, realize the function of more and more, the work frequency of the system is more and more high, the working frequency of DDR also gradually increased from the lowest 133 MHz to 200 MHz, so as to realize the system of the greater bandwidth and better performance. However, higher work frequency and at the same time put forward higher request to the stability of the system, this need hardware designers to the layout of the circuit line more constraints and considerations. And affect the whole system can work normal and stable is the most important part of the DDR part of the circuit design.

Embedded systems using DDR memory, can be in traditional single data rate memory chip to achieve better performance. DDR allowed without increasing clock frequency and data bits wide, under the condition of a clock cycle can handle two operations. Increase the performance of the data bus is due to the source synchronous data gating allows data at the same time in the rising and falling of strobe is acquired.

Although DDR can bring better performance to the embedded design, but the designer must SDR design more carefully than ever to deal with DDR parts of PCB wiring, otherwise not only cannot achieve good performance, the stability of the whole embedded type system would also be affected. DDR signals are shorter than traditional SDR to establish maintain time, cleaner closer walk line matching reference voltage, and the new I/O port signal, and need the right terminal resistance matching. These are facing new challenges.

1 DDR bus structure

For the DDR memory, JEDEC set up and use a standard low pressure high speed signal. The standard is called "stub series end Logic (StubSeries Terminated Logic, SSTL)". SSTL can improve data through bus transmission signal integrity, the terminal design purpose is to prevent under high-speed transmission error due to signal reflection data.

In a typical memory topology structure, if you use the series matching resistance (RS), then it should be placed away from the location of the DDR controller. This method can save valuable near controller circuit board space, avoid wiring congestion and tedious pin fan out; But also the optimization from the controller to the memory chip of signal integrity, in these positions tend to have a lot of need reliable by multiple memory address and command signal reception.

The most common SSTL terminal model is a good single terminal and terminal solution in parallel, as shown in figure 1. This scheme includes the use of a series resistor (Rs) from the controller to the memory, and a parallel resistor (RT) on the way to the terminal voltage (VTT). This method is common in business computer motherboard, but the current embedded motherboard in order to get a better signal integrity and system stability, and often use. The RS and the value of RT is depend on the specific system, specific value should be determined by the board level simulation.

2 analysis of embedded DDR wiring

2.1 DDR signal integrity problems

High speed bus signal transmission, often need to consider the signal integrity issues. DDR rather than ordinary signal transmission line, and a hole on a transmission line, or connector, discontinuous impedance factor will affect the signal at the receiving end. Main had rushed and rushed, ringing and crosstalk under the influence, ac noise and dc voltage inaccurate factors also affect the performance of the signal transmission.

DDR in order to achieve a higher frequency signal, SSTL high-gain differential receiver receiving level tend to be offset in the reference level (VREF) near the use of such a receiver to allow smaller voltage swing, less signal reflection, lower electromagnetic interference and the establishment of a shorter time, higher clock frequency than LVTTL can adapt. SSTL interface level is shown in figure 2. Communication logic level is the reception level on the receiver end, at the receiver communication logic parameters (including establish and maintain time) must be the best, while dc logic level provides a lagging reception level. When the input level through the DC DC reference point, receiver shift to a new logic level and keep the new state, as long as the signal is not lower than the threshold level. Therefore, not easy to be SSTL bus 

2.2 consider the DDR signals of grouping based on the wiring

DDR controller including more than 130 signals, and provides direct memory subsystem signal interface connection. These signals signals can be divided into different groups according to the types of signals, such as listed in table 1.

Data set of grouping should divided by each byte channel, DM0, DQS0 and DQ0 ~ is 1 byte channel, DQ7 DM1, DQS1 and DQ8 ~ DQ15 for channel 2 bytes, and so on. The length of each byte channel with strict matching relationship. Other signals go line length should be carried out in accordance with the group as the unit to match, the signal length difference in each group should be strictly controlled within a certain range. Between different groups of signal while not as strict as the signal in the group, but different length difference also has certain requirements. See section 2.4 specific wiring requirements.

2.3 wiring sequence signal group

In order to ensure the DDR interface optimization, DDR wiring should be carried out in accordance with the following order: power, resistance in the network exchange, data signal pin feet wiring, address/command signal wiring and control signal wiring, the clock signal wiring,

roup data signal wiring priority is the highest of all signal groups, because it works at twice the clock frequency, the signal is of the highest integrity requirements. In addition, the data signal groups are all of these signals in the memory bus accounted for the most part of the wide, also is the main line length matching requirements of signal group.

Group address, command, control and data signal are related to the clock go line. System, therefore, effective length of the clock go line should meet a variety of relations. Designers should establish system timing of comprehensive consideration, to ensure that all these relationships can be satisfied.

2.4 each signal wiring length matching

Clock signal: ground plane as the reference, to walk the whole clock circuit line provides a complete ground plane, to provide a low impedance of the loop current path. Due to the clock signal is difference, should advance the design in a row before you go line line width line distance, the calculated difference impedance, again according to the constraint for wiring. All the DDR difference clock signal must be walking on the critical plane line, try to avoid conversion layer to layer. Line width difference spacing need to refer to the detailed rules for the implementation of DDR controller, signal of the single line impedance should be controlled in 50 ~ 60 次, differential impedance control 次 in 100 ~ 100. The clock signal to the other signal should keep at a distance of more than 20 mil * to prevent interference with other signals.Series resistor RS values in 15 ~ 33 次, optional parallel resistor RT value in 25 ~ 68 次, specific resistance should be set according to the signal integrity simulation results.

Data signal groups: ground plane as reference, to signal circuits provide complete ground plane. Characteristic impedance control in 50 ~ 60 次. Line width requirement refer to detailed rules for the implementation. At least 20 mil isolation and other non DDR signals spacing. Matching length in bytes channel set for the unit, each byte channel data signal DQ, gating and data masking signal DM DQS length difference should be controlled within + / - 25 mil (very important), different byte channel signal length difference should be controlled within 1 000 mil. With the DM and matching the DQS series matching resistance RS value is 0 ~ 33 次, parallel matching terminal resistance RT 次 value of 25 ~ 68. If use resistance line matching, data inside resistance row should not have other DDR signals.

The address and command signal groups: intact and power plane. Characteristic impedance control in 50 ~ 60 次. Line width refer to specific design rules. Signal group and other non DDR signals span at least keep in more than 20 mil. Signal in the group should be matching with the DDR clock line length, control the gap at least 25 mil. RS series matching resistance value of O ~ 33 次, parallel matching resistance RT value should be within 25 ~ 68 次. Don't within our group of signals and data signals within the group of resistance in the same row.

ignal control signal groups: control group of signals at least, only the clock can make and choose two signals. Still need to have a complete ground plane and the power plane for reference. RS series matching resistance value of O ~ 33 次, parallel matching terminal resistance RT 次 value of 25 ~ 68. In order to prevent crosstalk, nor does it within our group signals and data signals inside resistance in the same row

2.5 the power part of the design and analysis

Typically, DDR power supply voltage from 2.3 V to 2.7 V, typical value is 2.5 V, working frequency of different may cause normal working voltage. The voltage reference VREF is 1.13 ~ 1.38 V, typical value is 1.25 V. VTT VREF as reference, the voltage range is (VREF - 0.4 - V) - (VREF + 0.4 V). Due to VREF just give differential receiver end provides a dc reference level, so the current is small, only 3 largest mA. VTT, because of the pull on the current output in the output high electricity at ordinary times, the VTT should be able to flow into the current; On the output side output low electricity at ordinary times the VTT current output. So the VTT must be able to have the inflows and outflows current at the same time, with the size of the current depends on the bus

Due to VREF voltage as signal other important reference at the receiving end, therefore its wiring design is also very important. Overlay on the crosstalk or noise can directly lead to VREF voltage potential timing error memory bus, jitter and drift. Many power supply chip will put VREF and VTT output from the same source, but due to the use, the different aims of walk line also is completely different. VREF and best VTT in different plane, lest the noise produced by the VTT VREF. And whether in the side or DDR memory DDR controller, VREF feet should be placed near the decoupling capacitor, eliminate the high frequency noise. VREF walk line width should be as wide as possible, the best is 20 ~ 25 mil.

VTT power should be a separate partition a plane to supply current, and the best in the DDR memory. If parallel termination to use exclusion in the way, it is best add a 0.1 u F every exclusion or 0.01 u F decoupling capacitor, this to improve the signal integrity, improve the stability of the DDR bus has good effect.


In the embedded system with DDR motherboard, design of PCB is one of the most difficult part of the DDR line design. Good go line is to have a good signal integrity and timing matching, bus during high speed input/output data will not make a mistake, even can have a better ability to resist crosstalk and EMC. DDR bus parallel transmission and high speed in the design process if not carried out in accordance with the strict constraints wiring, in the process of late equipment debugging, there will be a variety of unusual problems, even the system cannot boot. While these problems may be difficult to find in the find and debugging, to complete the development of the hardware.The best way is to design for full consideration of signal integrity and timing matching problem, go on line in applying these rules; If there is a condition, can do a simulation, verify the design in advance. So that make to design, stability and reliability of the system will be higher.

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